In a synchronous integrated circuit (IC), a clock signal is routed from an internal clock generator or an external clock input signal to registers and other circuits in order to control the sequences and timing of control and data operations therein. Clocked storage devices, such as flip-flops, latches, registers and other clocked storage circuits, and their respective clock input may be referred to herein as a sink or clock sink. Ideally, a clock signal should arrive at all the sinks at exactly the same time. However in reality, the clock signal arrives at different times at different sinks such as from asymmetries in clock drivers/buffers, the clock distribution network, loading, process variations, and interconnect delays. The difference between the arrival times of the clock signal at different sinks is called clock skew. More particularly, clock skew is the phase shift in a single clock distribution network resulting from the different delays in the clock signal to different sinks.
Unintentional clock skew is an undesirable effect in synchronous circuits in which the clock signal arrives at the registers at times different from the desired times. During logic synthesis of an integrated circuit, clock skew is considered a parasitic effect and is thus included in the design margin. However with ever increasing clock frequencies and performance requirements in today's application specific integrated circuits, the design margin required to cover clock skews due to process variations and interconnect delays can become significant.
Unintentional clock skew has become an expensive overhead that can reduce design margins and may negatively impact an integrated circuits' performance and robustness to process variations. If unintentional clock skew can be reduced during logic synthesis, a more optimized design of an integrated circuit may be achieved.